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MC100LVEP14 Low-Voltage 1:5 Differential LVECL/LVPECL/LVEPECL/HSTL Clock Driver
The MC100LVEP14 is a low skew 1-to-5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The LVECL/LVPECL input signals can be either differential or single-ended (if the VBB output is used). HSTL inputs can be used when the LVEP14 is operating under LVPECL conditions. The LVEP14 specifically guarantees low output-to-output skew. Optimal design, layout, and processing minimize skew within a device and from lot to lot. To ensure that the tight skew specification is realized, both sides of any differential output need to be terminated identically into 50W even if only one side is being used. When fewer than all five pairs are used, identically terminate all the output pairs on the same package side whether used or unused. If no outputs on a single side are used, then leave these outputs open (unterminated). This will maintain minimum output skew. Failure to do this will result in a 10-20ps loss of skew margin (propagation delay) in the output(s) in use. The common enable (EN) is synchronous, outputs are enabled/ disabled in the LOW state. This avoids a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input. The MC100LVEP14, as with most other LVECL devices, can be operated from a positive VCC supply in LVPECL mode. This allows the LVEP14 to be used for high performance clock distribution in +3.3V or +2.5V systems. Single ended input operation is limited to a VCC 3.0V in LVPECL mode, or VEE -3.0V in LVECL mode. Designers can take advantage of the LVEP14's performance to distribute low skew clocks across the backplane or the board. For more information, refer to Application Note AN1406/D.
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1
TSSOP-20 DT SUFFIX CASE 948E
MARKING DIAGRAM*
VP = LVEP 100 VP14 ALYW A L Y W = Assembly Location = Wafer Lot = Year = Work Week
*For additional information, see Application Note AND8002/D
ORDERING INFORMATION
Device MC100LVEP14DT Package TSSOP Shipping 75 Units/Tray 2500 Tape & Reel
* * * * * * * * * * * *
100ps Part-to-Part Skew 25ps Output-to-Output Skew Differential Design 400ps Typical Propagation Delay High Bandwidth to 1.5 Ghz Typical LVPECL and HSTL mode: +2.375V to +3.8V VCC with VEE = 0V LVECL mode: 0V VCC with VEE = -2.375V to -3.8V 75k Internal Pulldown CLKs, Pull up & Pulldown CLKs ESD Protection: >2KV HBM; >100V MM Moisture Sensitivity Level 2 For Additional Information, See Application Note AND8003/D Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34 Transistor Count = 357 devices
MC100LVEP14DTR2 TSSOP
(c) Semiconductor Components Industries, LLC, 2000
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May, 2000 - Rev. 1
Publication Order Number: MC100LVEP14/D
MC100LVEP14
VCC 20 EN 19 VCC 18 CLK1 CLK1 17 16 1 VBB CLK0 CLK0 CLK_SEL VEE 15 0 14 13 12 11
DQ
1 Q0
2 Q0
3 Q1
4 Q1
5 Q2
6 Q2
7 Q3
8 Q3
9 Q4
10 Q4
Figure 1. 20-Lead TSSOP and Logic Diagram (Top View)
Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
PIN DESCRIPTION
Pins CLK0, CLK0 CLK1, CLK1 Q0:4, Q0:4 CLK_SEL EN VBB VCC VEE Function LVECL/LVPECL/HSTL CLK Input LVECL/LVPECL/HSTL CLK Input LVECL/LVPECL Outputs LVECL/LVPECL Active Clock Select Input Sync Enable Reference Voltage Output Positive Supply Negative, 0 Supply
FUNCTION TABLE CLK0 L H X X X CLK1 X X L H X CLK_SEL L L H H X EN L L L L H Q L H L H L*
* On next negative transition of CLK0 or CLK1
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MAXIMUM RATINGS*
Symbol VEE VCC VI VI Iout IBB TA Tstg JA JC Tsol Power Supply (VCC = 0V) Power Supply (VEE = 0V) Input Voltage (VCC = 0V, VI not more negative than VEE) Input Voltage (VEE = 0V, VI not more positive than VCC) Output Current VBB Sink/Source Current{ Operating Temperature Range Storage Temperature Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Solder Temperature (<2 to 3 Seconds: 245C desired) Still Air 500lfpm Continuous Surge Parameter Value -6.0 to 0 6.0 to 0 -6.0 to 0 6.0 to 0 50 100 0.5 -40 to +85 -65 to +150 90 60 30 to 35 265 Unit VDC VDC VDC VDC mA mA C C C/W C/W C
* Maximum Ratings are those values beyond which damage to the device may occur. { Use for inputs of same package only.
DC CHARACTERISTICS, ECL/LVECL (VCC = 0V, VEE = -3.3(+0.925, -0.5)V) (Note 5.)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL 1. 2. 3. 4. 5. Characteristic Power Supply Current (Note 1.) Output HIGH Voltage (Note 2.) Output LOW Voltage (Note 2.) Input HIGH Voltage Input LOW Voltage Output Reference Voltage (Note 3.) Input HIGH Voltage Common Mode Range (Note 4.) Input HIGH Current Input LOW Current 0.5 -150 Min 45 -1145 -1995 -1165 -1810 -1525 -1425 VEE + 1.2 Typ 60 -1020 -1820 Max 75 -0895 -1650 -0880 -1625 -1325 0.0 150 0.5 -150 Min 45 -1145 -1995 -1165 -1810 -1525 -1425 VEE + 1.2 25C Typ 60 -1020 -1820 Max 75 -0895 -1650 -0880 -1625 -1325 0.0 150 0.5 -150 Min 45 -1145 -1995 -1165 -1810 -1525 -1425 VEE + 1.2 85C Typ 60 -1020 -1820 Max 95 -0895 -1650 -0880 -1625 -1325 0.0 150 150 Unit mA mV mV mV mV mV V A A
VCC = 0V, VEE = VEEmin to VEEmax, all other pins floating. All loading with 50 ohms to VCC-2.0 volts. Single ended input operation is limited VEE -3.0V in ECL/LVECL mode. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. Input and output parameters vary 1:1 with VCC.
DC CHARACTERISTICS, HSTL (VCC = 2.5(-0.125, +1.3)V, VEE = 0V)
-40C Symbol VIH VIL VX Characteristic Input HIGH Voltage Input LOW Voltage Input Crossover Voltage 100 680 100 Min Typ Max Min 1200 400 900 100 25C Typ Max Min 85C Typ Max Unit mV mV mV mA
ICC Power Supply Current (Note 6.) 6. VCC = 2.375V to 3.8V, VEE = 0V, all other pins floating.
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MC100LVEP14
DC CHARACTERISTICS, LVPECL (VCC = 3.3V 0.5V, VEE = 0V) (Note 11.)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current (Note 7.) Output HIGH Voltage (Note 8.) Output LOW Voltage (Note 8.) Input HIGH Voltage Input LOW Voltage Output Reference Voltage (Note 9.) Input HIGH Voltage Common Mode Range (Note 10.) Input HIGH Current Input LOW Current 0.5 -150 Min 45 2155 1305 2135 1490 1775 1.2 1875 Typ 60 2280 1480 Max 75 2405 1650 2420 1675 1975 3.3 150 0.5 -150 Min 45 2155 1305 2135 1490 1775 1.2 1875 25C Typ 60 2280 1480 Max 75 2405 1650 2420 1675 1975 3.3 150 0.5 -150 Min 45 2155 1305 2135 1490 1775 1.2 1875 85C Typ 60 2280 1480 Max 75 2405 1650 2420 1675 1975 3.3 150 150 Unit mA mV mV mV mV mV V A A
7. VCCmin to VCCmax. 8. All loading with 50 ohms to VCC-2.0 volts. 9. Single ended input operation is limited VCC 3.0V in PECL mode. 10. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. 11. Input and output parameters vary 1:1 with VCC.
DC CHARACTERISTICS, LVEPECL (VCC = 2.5V 0.125V, VEE = 0V) (Note 15.)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR IIH IIL Characteristic Power Supply Current (Note 12.) Output HIGH Voltage (Note 13.) Output LOW Voltage (Note 13.) Input HIGH Voltage Input LOW Voltage Input HIGH Voltage Common Mode Range (Note 14.) Input HIGH Current Input LOW Current 0.5 -150 Min 45 1355 505 1335 690 1.2 Typ 60 1480 680 Max 75 1605 850 1620 875 2.5 150 0.5 -150 Min 45 1355 505 1335 690 1.2 25C Typ 60 1480 680 Max 75 1605 850 1620 875 2.5 150 0.5 -150 Min 45 1355 505 1335 690 1.2 85C Typ 60 1480 680 Max 75 1605 850 1620 875 2.5 150 150 Unit mA mV mV mV mV V A A
12. VCCmin to VCCmax. 13. All loading with 50 ohms to VEE. 14. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. 15. Input and output parameters vary 1:1 with VCC.
AC CHARACTERISTICS (VCC = 0V; VEE = -2.5(+0.125, -1.3)V)
-40C Symbol fmaxLVPECL fmaxHSTL tPLH tPHL tskew tJITTER VPP tr/tf Characteristic Maximum Input Frequency for LVECL and LVPECL Maximum Input Frequency for HSTL Propagation Delay to Output IN (differential) IN (single-ended) Within-Device Skew Part-to-Part Skew (Diff) Cycle-to-Cycle Jitter Minimum Input Swing Output Rise/Fall Time (20%-80%) 150 100 275 Min Typ 1.5 250 Max Min 25C Typ 1.5 250 Max Min 85C Typ 1.5 250 Max Unit GHz MHz ps 375 TBD TBD TBD 800 165 1200 250 150 110 475 300 400 400 25 100 TBD 800 180 1200 275 150 110 500 35 300 430 TBD TBD TBD 800 200 1200 290 550 ps ps mV ps
16. Fmax guaranteed for functionality only. 17. Skew is measured between outputs under identical transitions.
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MC100LVEP14
PACKAGE DIMENSIONS
TSSOP-20 DT SUFFIX 20 PIN PLASTIC TSSOP PACKAGE CASE 948E-02 ISSUE A
20X
K REF
M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
K K1 J J1
L
PIN 1 IDENT 1 10
B -U-
SECTION N-N
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
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IIII IIII IIII
0.25 (0.010) M DETAIL E
2X
L/2
20
11
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
DIM A B C D F G H J J1 K K1 L M
MC100LVEP14
Notes
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MC100LVEP14
Notes
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MC100LVEP14
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MC100LVEP14/D

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